(a) Fields of the Invention
The present invention relates to nitride semiconductor devices applicable to power transistors for use in power supply circuits, and to their fabrication methods.
(b) Description of Related Art
In recent years, field effect transistors (FETs) made of gallium nitride (GaN)-based compound semiconductor materials have been actively studied as high-frequency, high-power devices.
Since nitride semiconductor materials such as GaN can form various types of mixed crystals such as aluminum nitride (AlN) and indium nitride (InN), they can form heterojunctions like conventional arsenic-based semiconductor materials such as gallium arsenide (GaAs). In particular, the heterojunction composed of the nitride semiconductor is characterized in that even with no doping performed thereon, high concentrations of carriers are generated at its interface by spontaneous polarization or piezoelectric polarization. As a result of this, in the case where a FET is fabricated from this material, the fabricated FET is likely to exhibit depletion type (normally-on type) characteristics, and hence it is difficult for the FET to exhibit enhancement-type (normally-off type) characteristics. However, most devices currently used in the power electronics market are normally-off type devices, so that normally-off type GaN-based nitride semiconductor devices are strongly demanded.
Approaches to attain normally-off type transistors include: use of the structure in which a gate portion is dug to shift a threshold voltage positively (see, for example, T. Kawasaki et al., “Solid State Devices and Materials 2005 tech. digest”, pp. 206); use of the structure in which a FET is fabricated on the (10-12) plane of the orientation in a sapphire substrate to prevent a polarization electric field from being generated in the crystal growth direction of the nitride semiconductor (see, for example, M. Kuroda et al., “Solid State Devices and Materials 2005 tech. digest”, pp. 470); and the like. As a potential structure for realizing the normally-off type FET, a junction field effect transistor (JFET) is proposed in which a p-type GaN layer is formed in a gate portion (see, for example, Japanese Unexamined Patent Publication No. 2005-244072). In this specification, the minus sign “−” attached to Miller indices included in the orientation represents the reversal of the index following the minus sign for convenience.
In the JFET structure, piezoelectric polarization generated at a first heterointerface between a channel layer of undoped GaN and a barrier layer of undoped AlGaN is cancelled by another piezoelectric polarization generated at a second heterointerface between the AlGaN barrier layer and a p-type GaN layer formed on the AlGaN barrier layer. This selectively decreases the concentration of two-dimensional electron gas immediately below a gate portion formed with the p-type GaN layer, whereby the JFET with normally-off characteristics can be provided. In addition, by employing, in the gate electrode, a pn junction having a higher built-in potential than a Schottky junction composed of metal and semiconductor, gate turn on voltage can be raised. This provides an advantage that even though a positive gate voltage is applied, a gate leakage current can be reduced to a low value.
However, as a result of fabrication of the conventional JFET as shown in FIG. 11, the inventors of the present invention found out the fact that a drain current decreases when a high drain voltage is applied, that is, a so-called current collapse occurs.
As shown in FIG. 11, the conventional JFET made of a nitride semiconductor includes a buffer layer 102 of AlN, a channel layer 103 of undoped GaN, a barrier layer 104 of undoped AlGaN, and a p-type GaN layer 105, which are sequentially formed on a substrate 101 of sapphire. The p-type GaN layer 105 is selectively provided between the barrier layer 104 and a gate electrode 108.
On regions of the barrier layer 104 located on both sides of the gate electrode 108, a source electrode 106 and a drain electrode 107 are formed to be spaced apart from the gate electrode 108. In this structure, the gate electrode 108 is made of, for example, palladium (Pd), and is in ohmic contact with the GaN layer 105. The source electrode 106 and the drain electrode 107 are each formed of a film made by stacking titanium (Ti) and aluminum (Al) from the substrate side.
FIG. 12 shows the relation between the drain current Id and the drain voltage Vds, which is obtained when pulse voltages having the same cycle are applied to the gate electrode 108 and the drain electrode 107 of the conventional JFET shown in FIG. 11, respectively. In this figure, the pulse width of the pulse voltage applied to the gate electrode 108 and the drain electrode 107 is set at 0.5 μs, and the pulse interval is set at 1 ms.
In FIG. 12, the plot A is obtained in the case where as a bias condition prior to application of a pulse voltage, both of the gate voltage and the drain voltage are 0 V, while the plot B is obtained in the case where as the bias condition, the gate voltage is 0 V and the drain voltage is 60 V. As shown in FIG. 12, for example, in the case of the plot B where the gate voltage Vgs is 5 V and the drain voltage Vds is 10 V, the drain current Id decreases by about 90 mA/mm as compared with the case of the plot A where the gate voltage Vgs is 5 V and the drain voltage Vds is 10 V. From this result, it is found that if a high drain voltage is applied to the drain electrode 107 prior to application of the bias voltage, the on-resistance increases. This phenomenon is the so-called current collapse. Since the occurrence of the current collapse significantly increases the on-resistance, this becomes an extremely serious problem for a power transistor to which a high drain voltage is applied.